A flash memory is a type of Programmable Read Only Memory (PROM) allowing electrical rewriting of data. Flash memory is a device that is designed to perform the programming method of an Erasable PROM (EPROM) and the erase method of an Electrically Erasable PROM (EEPROM) using a single transistor. An EPROM has an advantage in that a memory cell is implemented using a single transistor and thus the cell area is small, but has a disadvantage in that data stored in the EPROM must be simultaneously erased using ultraviolet rays. An EEPROM, however, is electrically erasable, but has a disadvantage in that a memory cell is composed of two transistors, and thus the cell area is large. A flash memory combines the advantages of both the EPROM and the EEPROM.
The exact name of flash memory is flash EEPROM. Since such flash memory retains stored information even when power is turned off, it is called non-volatile memory, and is different from Dynamic Random Access Memory (DRAM) or Static RAM (SRAM) in this regard.
A flash memory can be classified according to the structure of its cell array into a NOR-type flash memory, in which cells are arranged in parallel between a bit line and a ground, and a NAND-type flash memory, in which cells are arranged in series between a bit line and a ground. The NOR-type flash memory, having a parallel structure, is widely used for booting mobile phones because high-speed random access is possible during a read operation. The NAND-type flash memory, having a series structure, is advantageous in that it is generally suitable for storing data because, although the reading speed thereof is low, the writing speed thereof is high, providing profitability through miniaturization.
Furthermore, flash memory can be classified into stacked gate-type flash memory and split gate-type flash memory according to the structure of a unit cell, and can be classified into a floating gate device and a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device according to the type of a charge storage layer.
The floating gate device includes a floating gate made of polycrystalline silicon surrounded by a dielectric, and is operated to store or erase data by injecting or discharging charges into, or from, the floating gate through channel hot carrier injection or Fowler-Nordheim (F-N) Tunneling.
FIG. 1A is a sectional view showing a typical NOR-type flash memory device. The section of the device in FIG. 1A represents the vertical section of the flash memory device parallel to a word line. In the conventional flash memory device, a series of device isolations 12, for example, Shallow Trench Isolations (STIs), are formed in a substrate 10 in a direction perpendicular to the word line, thus active device regions are defined. Thereafter, silicon oxide layers 14, used as tunnel oxide layers, are formed in the active device regions of the substrate 10 at a certain thickness, and then a polycrystalline silicon layer, which will be used as a floating gate, is formed. The polycrystalline silicon layer, formed in this way, is patterned through a photo process and an etching process, thus an array of floating gates 16a is formed. In addition, an inter-gate dielectric layer 20 and a control gate 22, made of a polycrystalline silicon layer, are sequentially formed on the floating gates 16a that are spaced apart from each other by a predetermined distance, thus completing a stacked gate.
The above-described conventional process for manufacturing a flash memory device is performed in such a way that, after STIs are formed in the substrate, floating gates are patterned through a separate photo process. In this case, the floating gates and active device regions overlap each other, as shown in region A of FIG. 1A. The reason for this is to secure an overlap margin for the photo process. However, the size of the unit cell increases due to this overlapping region. That is, as shown in FIG. 1B, the overlapping region has an area of about 10.5F2 (where F is a one-dimensional unit for comparison). In FIG. 1B, reference numeral 22 denotes a control gate constituting a word line, reference numeral 30 denotes an active device region, and reference numeral 32 denotes a drain contact.
As a method of further reducing the size of a unit cell, a Self-Aligned STI (SA-STI) process has recently been developed. According to this method, a process for forming STI and a process for patterning floating gates can be performed as a single process. That is, after a tunnel oxide layer and a floating gate-forming layer are formed first on a substrate, the floating gate-forming layer, the tunnel oxide layer and part of the substrate are simultaneously etched using a mask oxide layer, thus forming a trench in the substrate. Next, the trench is covered with an oxide layer, and then an STI is formed.
According to this method, since the side walls of a floating gate pattern are aligned with the STI, the area of a unit cell can be reduced. However, the trench in the SA-STI process is formed deeper than the trench in a typical STI process. Accordingly, it is difficult to fill the trench with an oxide, and it is also difficult to apply the SA-STI process to the case where a memory cell and a logic cell are formed together in a single device because the process for forming the trench is different from a typical STI formation process. Furthermore, when a Chemical-Mechanical Polishing (CMP) process is applied after the gap-filling of STI has been terminated the floating gate and the tunnel oxide layer may be damaged. If the CMP process is not applied, it is difficult to perform planarization, thus a problem may occur in a subsequent process.